1. Field
Embodiments of the present invention relate to a buffer, and, more specifically, a current mode logic (CML) buffer with improved fall time and rise time characteristics.
2. Related Art
A logic buffer is a non-linear amplifier that is configured to map possible analog input voltages into one of two output voltages (e.g., an output signal corresponding to a logic signal of “low” or “high”). Current mode logic may be used for high-speed signal transmission and for circuit interfacing. Accordingly, high-performance CML buffers are widely accepted for various electronic applications, such as high-sped serial interfaces, because of the ability of CML buffers to achieve high speeds.
A CML buffer may be implemented as a differential pair amplifier with load resistors. The rise and fall times of the CML buffer, which may be respectively measured as an amount of time required for a signal to rise to 80% of the final output voltage, or to fall to 20% of the final output voltage, may be approximated as a function of resistance of the load resistors and a total load capacitance. For example, the rise and fall time of a Related Art CML buffer can be approximated as 1.6*Rload*Cload, where Rload is the resistance of the output load resistors, and Cload is the total load capacitance.
In measuring the rise and fall time of a CML buffer, an eye diagram may be used to analyze the performance of the CML buffer, and may be constructed from a time-domain waveform by folding parts of the waveform corresponding to each individual bit into a single graph (e.g., the graph having a measured signal amplitude corresponding to a vertical axis, and having time corresponding to a horizontal axis).
The above information disclosed in this Background section is only to enhance the understanding of the background of the invention and therefore it may contain information that does not constitute prior art.